National Institute Of Technology,Kurukshetra

DEPARTMENT OF ELECTRONICS&COMMUNICATION ENGG.

Faculty

Name : Gaurav Saini
Designation : Assistant Professor
Qualification : Ph.D. (NIT Kurukshetra) M. Tech. (NIT Hamirpur)
Current Address :

Room No. 123, Deptt. of ECE NIT Kurukshetra Haryana, INDIA

 

 


Phone 1 (office) : 01744-233141
Phone 2 (office) : 8950461132
Email : gauravsaini@nitkkr.ac.in, gaurav.nitham@gmail.com

Area Of Intrest :

Students who would like to purse Ph.D. or any research-oriented work with me, are always welcome.

Microelectronics, Nanoscale VLSI Devices, Low Power VLSI Design

Experience :

  • Teaching and Research: 10+ Years

Other :

Web Reference: Google Scholar

  1. List of publications:
  1. International Referred Journal:
  1. Muktasha Maji, Gaurav Saini, “Modeling of dual material surrounding split gate junctionless transistor as biosensor”, Superlattices and Microstructures, Volume 135, 2019, 106290, ISSN 0749-6036. (SCI listed)
  2. Abhinav Chauhan, Gaurav Saini, Pavan Kumar Yerur, “Improving the performance of dual-k spacer underlap Double Gate TFET, Superlattices and Microstructures, vol. 124, pp. 79-91, 2018. (SCI listed)
  3. G. Saini and S. Choudhary, "Investigation of trigate JLT with dual-k sidewall spacers for enhanced analog/RF FOMs," Journal of Computational Electronics (Springer), vol. 15, pp. 865-873, 2016. DOI: 10.1007/s10825-016-0866-6 (SCI listed)
  4. G. Saini and S. Choudhary, "Analog/RF performance of source-side only dual-k sidewall spacer trigate junctionless transistor with parametric variations," Superlattices and Microstructures (Elsevier), vol. 100, pp. 757-766, 2016. https://doi.org/10.1016/j.spmi.2016.10.037 (SCI listed)
  5. G. Saini and S. Choudhary, "Improving the performance of SRAMs using asymmetric junctionless accumulation mode (JAM) FinFETs," Microelectronics Journal (Elsevier), vol. 58, pp. 1-8, 2016. https://doi.org/10.1016/j.mejo.2016.10.004 (SCI listed)
  6. G. Saini and S. Choudhary, "Improving the subthreshold performance of junctionless transistor using spacer engineering," Microelectronics Journal (Elsevier), vol. 59, pp. 55-58, 2017. https://doi.org/10.1016/j.mejo.2016.11.012 (SCI listed)
  7. G. Saini and S. Choudhary, "Asymmetric dual-k spacer trigate FinFET for enhanced analog/RF performance," Journal of Computational Electronics (Springer), vol. 15, pp. 84-93, 2016. DOI: 10.1007/s10825-015-0769-y (SCI listed)
  8. Swati Choudhary and Gaurav Saini, “A Hetero-Spacer-Dielectric Double-Gate Junctionless Transistor for Enhanced Analog Performance,” Int. Journal of Electrical & Electronics Engg. vol. 2, spl. issue 1, pp. 66-70, 2015.
  9. Sudhanshu Choudhary, Gaurav Saini and S. Qureshi, "Impact of Radial Compression on the Conductance of Carbon Nanotube Field Effect Transistors," Modern Physics Letters B, (World Scientific Publication), vol. 28, no.2, pp. 1-9, 2014. DOI: http://dx.doi.org/10.1142/S0217984914500079 (SCI listed)
  10. Gaurav Saini & Ashwani K Rana, “Physical Scaling Limits of FinFET Structure: A Simulation Study,” International Journal of VLSI design & Communication Systems (VLSICS) Vol.2, No.1, March 2011, pp. 26-35.

 

  1. International Conferences
  1. M. Maji and G. Saini, "Performance Enhancement of Non-uniformly Doped Junctionless Transistors by Gate and Dielectric engineering," 2019 Devices for Integrated Circuit (DevIC), Kalyani, India, 2019, pp. 484-488.
    doi: 10.1109/DEVIC.2019.8783415
  2. N. Saini and G. Saini, "Spacer Engineered Junction-Less Transistor: A Device Circuit Co-Design Study for Ultra-Low Power Applications," 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2018, pp. 1445-1450.
    doi: 10.1109/ICCONS.2018.8662977
  3. S. Bharti and G. Saini, "Sensitivity Analysis of Junctionless FinFET for Analog Applications," 2018 Second International Conference on Intelligent Computing and Control Systems (ICICCS), Madurai, India, 2018, pp. 1288-1293.
    doi: 10.1109/ICCONS.2018.8662918
  4. U. Singh, G. Saini and N. Singh, "An Efficient Model to Count Objects in Motion by Trading Off the Area Threshold," 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore, India, 2018, pp. 484-487.
    doi: 10.1109/ICIRCA.2018.8597418
  5. S. Sai Charan and G. Saini, "Pedestrian Detection System with a Clear Approach on Raspberry Pi 3," 2018 International Conference on Inventive Research in Computing Applications (ICIRCA), Coimbatore, India, 2018, pp. 601-604.
    doi: 10.1109/ICIRCA.2018.8597306
  6. S. Rani and G. Saini, "Impact of Channel Engineering on Double Gate Junction Less Transistor for Improved Analog Performance," 2018 International Conference on Emerging Trends and Innovations In Engineering And Technological Research (ICETIETR), Ernakulam, 2018, pp. 1-6.
  7. Varsha Pathak, Gaurav Saini, “A Graded Channel Dual-Material Gate Junctionless MOSFET for Analog Applications,” Procedia Computer Science, Volume 125, 2018, Pages 825-831, ISSN 1877-0509, https://doi.org/10.1016/j.procs.2017.12.105.
  8. N. Chahal and G. Saini, "Analog performance investigation of double gate junctionless transistor using spacer layer engineering," 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, 2017, pp. 1-4.doi: 10.1109/ICCCNT.2017.8204086
  9. S. Dwivedi and G. Saini, "Effect of random dopant fluctuation in nanoscale junctionless FinFET using low and high-k spacers," 2017 8th International Conference on Computing, Communication and Networking Technologies (ICCCNT), Delhi, India, 2017, pp. 1-4.
    doi:10.1109/ICCCNT.2017.8204094
  10. S. K. Pandey and G. Saini, "Study of self-heating effects on fully depleted SOI MOSFETs with BOX layer engineering," 2017 International Conference on Trends in Electronics and Informatics (ICEI), Tirunelveli, 2017, pp. 962-965.
    doi: 10.1109/ICOEI.2017.8300850
  11. N. Gehlawat and G. Saini, "Random dopant induced threshold voltage variation analysis of asymmetric spacer FinFETs," 2017 International Conference on Trends in Electronics and Informatics (ICEI), Tirunelveli, 2017, pp. 953-956.
    doi: 10.1109/ICOEI.2017.8300848
  12. M. Madhini and G. Saini, "Heterojunction tunnel FET with Heterodielectric BOX," International Conference on Communication and Signal Processing (ICCSP), Melmaruvathur, 2016, pp. 1743-1746.
  13. Rohit and Gaurav Saini, “A Stable and Power Efficient SRAM Cell,” IEEE International Conference on Computer Communication and Control (IC4­2015) organized by Medi-Caps Group of Institutions, Indore, M.P. India, pp. 117-121, 2015.
  14. Devendra Jakhar and Gaurav Saini, “Design of a novel regulated cascode current mirror,” IEEE International Conference on Computer Communication and Control (IC4-2015) organized by Medi-Caps Group of Institutions, Indore, M.P. India, pp. 438-441, 2015.
  15. Bhargav, K.N.; Suresh, A.; Saini, Gaurav, "Stacked keeper with body bias: A new approach to reduce leakage power for low power VLSI design," Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on , vol., no., pp.445,450, 8-10 May 2014.
  16. Dillep, P.; Saini, Gaurav, "Enhanced cascode node impedance to the improved recyclic folded cascode OTA," Advanced Communication Control and Computing Technologies (ICACCCT), 2014 International Conference on , vol., no., pp.451,455, 8-10 May 2014.
  17. Gaurav Saini, Ashwani K Rana, Pankaj K Pal & Sunil Jadav “Leakage Behavior of Underlap FinFET structure: A Simulation Study,” in ICCCT-2010, International Conference of Computer and Communication Technology, organized by MNNIT Allahabad & sponsored by IEEE on September 17-19,2010, pp. 302-305.
  18. Gaurav Saini, Ashwani K Rana & Manoj Kumar “SOI Versus FinFET Structure: A Comparative Simulation Study, in ICACC-2011, International Conference on Advances in Computing and Communication organized by NIT Hamirpur & sponsored by IEEE on April 8-10, 2011, pp. 351-353.
  19. Pankaj K Pal, Rituraj S Rathod, Ashwani K Rana & GauravSaini “New Low-Power Techniques: Leakage Feedback with Stack & Sleep Stack with Keeper,” in ICCCT-2010, International Conference of Computer and Communication Technology, organized by MNNIT Allahabad &sponsored by IEEE on September 17-19,2010, pp. 296-301.
  20. Academic/Administrative Contributions:
  • Presently Nodal Officer MIS-Academic under TEQIP-3 since May 2019.
  • Presently Hostel Warden of Hostel No. 4.
  • Served as Hostel Warden of Hostel No. 8 during 2017-18 to 2018-19.
  • Served as Faculty In-charge of Embedded System and Robotic Control during 2017-18.
  • Presently Nodal Officer of ECE Department Website.
  • Presently Timetable In-charge of School of VLSI Design and Embedded Systems.
  • Served as Prof. In-charge of Advanced Electronics Lab.
  • Presently Prof. In-charge of VLSI Design and Microprocessor Lab.
  • Served as Committee member of National Board of Accreditation (NBA) of ECE Department.
  • Served as Deputy Superintendent of Centre-5 during end semester examination May/June-2016 and Nov/Dec. 2018.

 

  1. Seminars/conferences/STC/FDP/QIP etc. organized and participated

S. No.

Title

Venue

Period

Organized/ Participated

  1.  

5-Day workshop on MATLAB and Simulink

School of VLSI Design and Embedded Systems, NIT Kurukshetra

July 30 to August 3, 2018

 

 

 

 

Organized

(Jointly)

  1.  

Faculty Development Program

in VLSI Design using Xilinx & Mentor Graphics Tools

School of VLSI Design and Embedded Systems, NIT Kurukshetra

September 10-14, 2018

Organized

(Jointly)

  1.  

5-Day Training Programme / Workshop was organized on Visual TCAD

School of VLSI Design and Embedded Systems, NIT Kurukshetra

Feb. 25 to March 1, 2019.

Organized

 

  1.  

Startup Workshop

Government Engineering college, Bikaner

22-23 April, 2019

Organized

(Jointly)

  1.  

Introduction to Analog and Digital VLSI Design

IIT Guwahati

10th to 14th April 2017

Participated

  1.  

Modeling, Simulation of Nano-Transistors

IIT Kanpur

13th to 17th February 2017

Participated

  1.  

SMDP-C2SD Cadence Tool Training Programme

PSG Coimbatore

23rd to 25th January 2017

Participated

  1.  

Modeling, Simulation and Characterization of Nano-Transistors

IIT Kanpur

26th to 30th October 2015

Participated

  1.  

Use of Process Design Kit (PDK) of Semiconductor Laboratory for designing VLSI circuits

School of VLSI Design and Embedded Systems, NIT Kurukshetra

July 31st and August 1st 2015

Organized

(Jointly)

  1.  

Nanoscale Science and Engineering: Materials, Electronics, Photonics, Biosensors and Beyond

IIT Indore

23th to 25th June 2014

Participated

  1.  

Developments in VLSI Devices and Technology (DiVDAT-13)

NIT Hamirpur

24th to 28th June 2013

Participated

 

D. Projects and Thesis supervised and co-supervised within institute:

           M.Tech.          : 13

           B.Tech.           : 04